*  Host Bus: 1-lane 2.5 Gb/s PCI Express
   * Eight (8) isochronous transmit/receive contexts
   * Deep 8 Kbyte isochronous transmit/receive FIFO’s
   * Complies with 1394 OHCI draft 1.2
   * Three external 1394 ports
   * Bilingual ports with Screw Holes for Jackscrew Type Plug Cable

The FWB-PCIE1X21B combines an OHCI (Open Host Controller Interface) and a high-performance, standards-compliant PCI Express 1.1 host system interface to provide S800 1394b-2002 compliant throughput in a small PCB (Printed Circuit Board) and low power dissipation.

MultipleVCs (Virtual Channels) on the PCI Express link provide native support for QoS (Quality of Service) transmission for real-time and multimedia applications in a standards-based framework, ensuring compatibility with current and future operating systems.
Active-state power management allows dynamic power management during periods of reduced network activity.

Technical Specification
PCI Express:
   * Designed for compliance with PCI Express.
   * Multiple virtual channel (VC0,VC1 ) support fordiffe-rentiating 1394 isochronous traffic.
   * Supports eight user-programmable traffic classes.
   * 64-bit and 32-bit platform support.
   * Interrupts via legacy INTx interface or message sig-naled interrupt (MSI).
   * Supports PCI Express clock power management viaCLKREQN signal for form factors that support thisprotocol.
   * Supports all linkpowermanagement states (L0,L0s,L1,andL2/L3) and active state power management(ASPM).
   * Supports wake-up from a low-power state via in-bandbeacon signaling and side-band WAKE_N signal.

OHCI (Open Host Controller Interface)
   * Enhanced with the OHCI 1.2 draft specification for 1394b-2002 PHY full operational compliance.
   * OHCI 1.0 backwards compatible. Configurable via EEPROM to operate in either OHCI 1.0 or OHCI 1.1 mode.
   * 8 Kbyte isochronous transmit FIFO.
   * 4 Kbyte asynchronous transmit FIFO.
   * 8 Kbyte isochronous receive FIFO.
   * 8 Kbyte asynchronous receive FIFO.
   * Dedicated asynchronous and isochronous descriptor-based DMA engines.
   * Eight isochronous transmit contexts.
   * Eight isochronous receive contexts.
   * Supports parallel processing of incoming physical read and write requests.
   * Supports up to 48-bit addressing per OHCI specifica-tion for the physical DMA transfers.

1394b-2002 Link
   * Cycle master and isochronous resource manager capable.
   * Supports 1394a-2000 and 1394b-2002 acceleration features.

1394b-2002 PHY
   * Provides three IEEER 1394b-2002 compliant ports sup-porting 1394b-2002 speeds of 800 Mbits/s and 400Mbits/s while maintaining backward compatibility to IEEE 1394a-2000 speeds of 100 Mbits/s, 200Mbits/s, and 400 Mbits/s over 4.5 m copper.
   * Fully supports provisions of IEEE 1394a-2000 and 1394-1995 standards for high-performance serial bus.
   * Link is not required for hub operation.
   * Supports extended BIAS_HANDSHAKE time for enhanced interoperability with camcorders.
   * Does not require external filter capacitor for PLL.
   * Supports arbitrated short bus reset to improve utiliza-tion of the bus.
   * Supports ack-accelerated arbitration and fly-by concat-enation.
   * Supports PHY pinging and remote PHY access pack-ets.
   * Fully supports suspend/resume.

     Reports cable power fail interrupt when voltage at CPS ball falls below 7.5 V.

Number of Ports:
   * Three Bilingual P1394b Cable Ports with Screw Holes for Jackscrew Type Plug Cable

Bus Power Connector:
   * Big IDE 4-pin DC Power Connector

Operating System Requirements
   * Windows 2000/XP and Windows Server 2003
   * Mac OS 10.4.8 or later
   * Linux 2.6.X

Výrobek je dodáván s manuálem pouze v anglickém nebo německém jazyce.